Technology
A Rust daemon on Linux, Zephyr firmware on every card, a backplane with a shared clock and hardware triggers, and one spec that drives the daemon, the client and the agent tools.
Architecture
hil APIpytest pluginhil CLIhil-mcp serverbench page & timelineJUnit / coverage
Tests name DUT signals through a hil.toml wiring map, never slot numbers. The client, MCP tools and page build themselves from the bench's capability list at runtime.
Compiles a plan into schedules and trigger rules, assigns trigger lines automatically when a condition and its action sit on different modules, loads every module, then starts them together.
modkit is a C11 library with no heap: module state machine, timebase, scheduler, trigger rules, event ring, heartbeat and safe state. The same code runs on the MCU and in the virtual bench.
Log scale. Shorter is faster.
What's new here
A test becomes a plan: schedules and rules, checked before it runs. benchd loads every module completely, with no clock involved, then sends one start(t0). The bench records; the client judges, so old runs can be judged again.
Cross-module reactions in hardware. The compiler picks the line; the host assigns ownership and checks for stuck lines at arm time.
A module class is one YAML file. Commands, client attributes, MCP tools and viewer waveforms all come from it. Guard tests keep the engine free of class names.
Signals bound at request time, risk classes (observe, stimulate, fault, power), action budgets and expiry, tied to the lease of the person who approved them.
The real firmware library runs as simulated modules on a shared timebase with a simulated trigger backplane. CI and demos work before the hardware does.
Pinout, protocol, EEPROM format and reference firmware are open. Third-party cards load at runtime from their own spec.
Every run stores its plan, its events as Parquet and a manifest with a comparable key. Requirements map to tests and runs on the coverage page and in JUnit, and any run exports to VCD for GTKWave or Surfer.
Module lineup
The design rule: every module type holds hardware the others lack.
1.8 / 3.3 / 5 / 12 V, edge timestamps, pulses, PWM, pulls and high-Z.
TTL, RS-232 and RS-485, per-byte timestamps, pattern match, framing and parity faults.
Switchable termination, filters, and bus faults by corrupting chosen frame IDs.
Setpoint, current limit, µA meter and charge. Dropout and sag faults, alert rules.
Central or peripheral peer for the DUT. Link loss, packet loss, reconnect time.
An example third-party class, loaded at runtime from its own spec file.
LIN, analog I/O, relay matrix, I²C/SPI target emulation, logic capture on the shared timeline.
Design partner program
We're looking for 5–10 firmware teams who ship at least monthly and test on hardware by hand or with a DIY rig today. Paid pilots, early hardware and a direct line to the people building it.
Talk to us →